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SM8521
SM8521 CONTENTS
DESCRIPTION .............................................................. 2 FEATURES .................................................................... 2 PIN CONNECTIONS ..................................................... 3 BLOCK DIAGRAM ....................................................... 4 PIN DESCRIPTION ....................................................... 5 ABSOLUTE MAXIMUM RATINGS ............................. 6 RECOMMENDED OPERATING CONDITIONS ............. 6 DC CHARACTERISTICS ............................................. 7 SM85CPU ...................................................................... 8
Register Lineup Address Space ROM Area Register File Area RAM Area Data Format Bus Timing
INSTRUCTION SET .................................................... 51
Definition of Symbols Instruction Summary Addressing Mode
SYSTEM CONFIGURATION EXAMPLE .................. 55
SYSTEM CONTROL .................................................. 18
Oscillator Circuit Clock System Memory Map Hardware Reset Interrupt Function Standby Function
I/O PORTS ................................................................... 29 TIMER/COUNTERS .................................................... 30
Clock Timer Watchdog Timer Register (WDT)
LCDC/DMA .................................................................. 33
VRAM Configuration DMA Transfer Compound and Overwrite Mode Registers
SOUND GENERATOR ............................................... 41
Sound Waveform Register Registers
MMU ............................................................................. 45 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER (UART) INTERFACE ......................... 47
UART Transmit Data Register (URTT) UART Receive Data Register (URTR) UART Status Register (URTS) UART Control Register (URTC) Transfer Format
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SM8521
SM8521
DESCRIPTION
The SM8521 is a CMOS 8-bit single-chip microcomputer containing SM85CPU core and the required peripheral functions for dot matrix LCD display system. SM85CPU is an 8-bit High performance CPU with various addressing modes and High-efficiency instruction sets. SM85CPU is featured by allocating general registers on RAM to reduce overhead when calling subroutines. The peripheral functions and memory of SM8521 contain ROM, RAM, MMU, LCD controller, DMA, sound generator, timer, serial interface (UART) and PIO.
8-Bit Single-Chip Microcomputer (Controller For Hand-Held Equipment)
* I/O ports : Input/output 32 * Timer : 8 bits x 2 (with 8 bits prescaller) Clock timer x 1 (1 s or 1 min) Watchdog timer * MMU : In each 8 k-byte unit, external memory can be expanded up to MAX. 2 M bytes. * LCD controller : Display size 160 x 100 dots 160 x 160 dots 160 x 200 dots 200 x 100 dots 200 x 160 dots black & white 4 gradations (interframe elimination) VRAM 160 x 200 dot x 2 phases or 200 x 160 dot x 2 phases (required externally) * DMA : Transmission mode : ROM to VRAM, VRAM to VRAM, Extend RAM to VRAM, VRAM to Extend RAM Transmission data : Rectangle (Arbitrary size) * Sound generator : Arbitrary waveform x 2 (16-level tone, 32step/1-period waveform output) Noise x 1 channel * PIO : I/O 8-bit x 4 (In each 2 bits, I/O, pull-up and open-drain can be set.) IR carrier generator built-in. * UART : 1 channel Baud rate : Timer 0 output only (Timer 0 output/32)
FEATURES
* * * * * ROM capacity : 4 096 x 8 bits RAM capacity : 1 024 x 8 bits External memory expansion A RAM area is used as subroutine stack CPU core : * 8 bits x 8 ports (or 16 bits x 4 ports) and 16 bits x 4 ports general purpose register are used as accumulator, register pointer, and register index. * Instruction sets 67 (multiplication/division/bit manipulation instruction) * Addressing mode 23 types * System clock cycle 0.2 s (MIN.) at 10 MHz main clock cycle * System clock is variable by software (system clock can be optioned to 1/2, 1/4, 1/8, 1/16, 1/32 of main-clock and 1/2 of sub-clock.) Built-in main clock oscillator for system clock Built-in sub clock oscillator for real time clock Interrupts : Non-maskable interrupts x2 Maskable interrupts x8 Standby modes : Halt mode/Stop mode
* * *
*
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
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SM8521
* Serial interface : UART * Clock output * Supply voltage : 4.5 to 5.5 V * Packages : 128-pin QFP (QFP128-P-1420)
8-bit clock asynchronous x 1
PIN CONNECTIONS
126 SOUND 125 DOFFB 116 VA12 115 VA11 114 VA10
128-PIN QFP
128 GND 127 VR
TOP VIEW
103 VD0 113 VA9 112 VA8 111 VA7 110 VA6 109 VA5 108 VA4 107 VA3 106 VA2 105 VA1 104 VA0
121 XD0
120 XD1
119 XD2
118 XD3
122 XC
NC D7 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 9
117 YD
124 FR
123 LP
102 VD1 101 NC 100 NC 99 VD2 98 VD3 97 VD4 96 VD5 95 VD6 94 VD7 93 VCE0B 92 VCE1B 91 VRDB 90 VWRB 89 P37 88 P36 87 P35 86 P34 85 P33 84 P32 83 P31 82 P30 81 P27 80 P26 79 P25 78 P24 77 P23 76 P22 75 P21 74 P20 73 P17 72 P16 71 P15 70 P14 69 P13 68 P12 67 P11 66 NC 65 NC
A0 10 A1 11 A2 12 A3 13 A4 14 A5 15 A6 16 A7 17 A8 18 A9 19 A10 20 A11 21 A12 22 A13 23 A14 24 A15 25 A16 26 A17 27 A18 28 A19 29 A20 30 RDB 31 WRB 32 MCE0B 33 MCE1B 34 IOE0B 35 IOE1B 36 GND 37 GND 38
GND 39
OSC1 40
OSC2 41
NC 42
INTB 43
NMIB 44
RESETB 45
M0 46
M1 47
M2 48
VDD 49
RXDB 50
TXDB 51
P00 52
P01 53
P02 54
P03 55
P04 56
P05 57
P06 58
P07 59
X1 60
X2 61
GND 62
CLK 63
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P10 64
SM8521
BLOCK DIAGRAM
RDB WRB
VA0-VA12 VD0-VD7
SM85CPU
INTB NMIB
VRDB, VWRB
LCDC/DMA
VCE0B, VCE1B FR, LP, XC XD0-XD3 YD, DOFFB
RAM 1 k-BYTE RAM 4 k-BYTE
A0-A20 VR SOUND
D/A
SOUND GENERATOR
MMU BUS CONTROLLER
D0-D7 MCE0B, MCE1B IOE0B, IOE1B
RXDB TXDB
UART
TIMER 8-BIT : 2 CH CLOCK WATCHDOG TIMER
P0
P1
P2
P3
P00 P01 P02 P03 P04 P05 P06 P07
P10 P11 P12 P13 P14 P15 P16 P17
P20 P21 P22 P23 P24 P25 P26 P27
P30 P31 P32 P33 P34 P35 P36 P37
X1 X2 CLK
OSC
OSC1 OSC2
VDD
GND
RESETB
M0-2
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SM8521
PIN DESCRIPTION
PIN NAME D0-D7 A0-A20 MCE0B MCE1B IOE0B IOE1B RDB WRB NMIB INTB VD0-7 VA0-12 VCE0B VCE1B VRDB VWRB P00-P07 P10-P17 P20-P27 P30-P37 RxDB TxDB SOUND VR FR LP XC XD0-XD3 YD DOFFB X1 X2 CLK OSC1 OSC2 RESETB M0-M2 VCC, GND I/O I/O O O O O O O O I I I/O O O O O O I/O I/O I/O I/O I O O I O O O O O O I O O I O I I I FUNCTION External data bus External address bus Chip enable 0 (Mask ROM/flash memory) Chip enable 1 (SRAM) I/O enable 0 (address : FF00-FFFF) I/O enable 1 (address : FF00-FFFF) Read strobe Write strobe Non-maskable interrupt External interrupt VRAM data bus VRAM address bus VRAM chip enable 0 (A000-BFFF) VRAM chip enable 1(C000-DFFF) VRAM read strobe VRAM write strobe I/O port 0 I/O port 1 I/O port 2 I/O port 3 UART data input port UART data output port Sound output D/A converter reference voltage LCD drive waveform Display data latch pulse Display data clock Diaplay data Vertical timing Display off Main clock input Main clock output System clock output Subclock input Subclock output Reset Operation Mode (usually GND) Power supply
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SM8521
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage Input voltage Output voltage Output current Operating temperature Store temperature SYMBOL VDD VI VO IOH IOL TOPR TSTG High-level output current Low-level output current CONDITION RATING -0.3 to 6.5 -0.3 to VDD + 0.5 -0.3 to VDD + 0.5 4 4 -10 to +60 -40 to +140 UNIT V V V mA mA C C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply voltage System clock frequency Maximum main clock frequency Subclock frequency Operating temperature SYMBOL VDD fSYS CONDITION VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V RATING 4.5 to 5.5 16.384 k to 5 M 10 32.768 -10 to +60 UNIT V Hz MHz kHz C
fCK
fSUB TOPR
NOTE :
Be sure to RESETB when power on because internal signal reguires initialization. Normal operation is not guaranteed without hardware reset.
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SM8521
DC CHARACTERISTICS
PARAMETER SYMBOL VIH1 Input voltage VIL1 VIH2 VIL2 IIH1 Input current IIL1 IIL2 VOH1 VOL1 VIN = VDD, VDD = 5 V VIH = 0 V, VDD = 5 V VIN = 0 V, VDD = 5 V IOH1 = -1 mA, VDD = 5 V IOL1 = 10 mA, VDD = 5 V VR = VDD = 5 V VR = VDD = 5 V VR = VDD = 5 V fSYS = 5 MHz fSYS = 5 MHz, HALT mode fSUB oscillation, STOP mode fSUB stop, STOP mode CONDITION
(VDD = 4.5 to 5.5 V, TOPR = -10 to +60C)
MIN. 0.8 x VDD 0 VDD - 0.5 0.5 10 -10 -40 VDD - 0.5 0.5 8 0.05 30 15 30 1 10 0.10 45 18 70 6 -75 -150 TYP. MAX. VDD 0.2 x VDD UNIT V V A A V bits k V mA A A 6 7 8 9 10 NOTE 1 2 3 4 5
Output voltage Resolution D/A
Output resistance Combined tolerance IDD IDDH IDDS1 IDDS2
Supply current
NOTES :
1. Applicable pins : P00-P07, P10-P17, P20-P27, P30-P37, D0D7, VD0-VD7, X1, M0-M2 2. Applicable pins : RESETB, OSC1, RxDB, NMIB, INTB 3. Applicable pins : P00-P07, P10-P17, P20-P27, P30-P37, VD0-VD7, X1, M0-M2 (non-connected pull-up resistor) 4. Applicable pins : RESETB, P00-P07, P10-P17, P20-P27, P30-P37 (connected pull-resistor) 5. Applicable pins : P00-P07, P10-P17, P20-P27, P30-P37, D0D7, A0-A20, MCE0B, MCE1B, IOE0B, IOE1B, RDB, WRB, VA0-VA12, VCE0B, VCE1B, VWRB, TxDB, XC, LP, FR, CLK, XD0-XD3 6. No load condition, VDD = 5 V, main clock = 10 MHz 7. No load condition, VDD = 5 V, sub clock in active (32.768 kHz), VR = GND, input signal fixation. 8. No load condition, VDD = 5 V, sub clock in active (32.768 kHz), VR = GND, input signal fixation. Including LCD, DMA, sound generator and any part concerned with timer operation. 9. No load condition, VDD = 5 V, sub clock in active (32.768 kHz), VR = GND, input signal fixation. 10. No load condition, VDD = 5 V, OSC1 = GND, VR = GND, input signal fixation.
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SM8521
SM85CPU
The SM85CPU is an 8-bit CPU with an unique architecture, developed by SHARP, and the following features. General purpose register architectures * There are eight 8-bit general purpose registers (also serve as four 16-bit general purpose registers) and four 16-bit general purpose registers serve as accumulator, index register, or the pointer registers. General purpose register allocated at RAM * The general purpose registers access the RAM location by the register pointer RP. So pushing the register during an interrupt and passing parameter to subroutine can be executed in High speed. Refined instruction set * The instruction set contains total 67 members : 8 load instructions, 19 arithmetic instructions, 7 logic instructions, 9 program control (branch) instruction, 8 bit manipulation instructions, 8 rotate & shift instructions and 9 CPU control instructions. * There are powerful bit manipulation instructions includes plural bits transfer, logical operation between bits, and the bit test and jump instructions that incorporates a test and condition branch in the same instruction. (Refer to Table 1) * There are data transfer, arithmetic and conditional branch instructions for 16-bit. It can rapidly process the word-sized and long jump. * There are 8-bit x 8-bit16-bit multiplication and 16-bit x 16-bit16-bit remaining 8-bit division instructions. (Unsigned arithmetic) 23 address modes * The rich address modes provides optimal access to ROM, RAM and the register files. Illegal instruction detecting function * When an error code is detected, a non-maskable interrupt (NMI) will be generated. Standby function * There are two standby modes, HALT and STOP mode, and the mode can be changed by HALT instruction or STOP instruction respectively.
Table 1 Instruction summary TYPE Load instruction Arithmetic instruction Logic instruction Program control instruction Bit manipulation instruction Rotate & shift instruction CPU control instruction INSTRUCTION CLR, MOV, MOVM, MOVW, POP, POPW, PUSH, PUSHW ADC, ADCW, ADD, ADDW, CMP, CMPW, DA, DEC, DECW, DIV, EXTS, INC, INCW, MULT, NEG, SBC, SBCW, SUB, SUBW AND, ANDW, COM, OR, ORW, XOR, XORW BBC, BBS, BR, CALL, CALS, DBNZ, IRET, JMP, RET BAND, BCLR, BCMP, BMOV, BOR, BTST, BSET, BXOR RL, RLC, RR, RRC, SLL, SRA, SRL, SWAP COMC, CLRC, DI, EI, HALT, NOP, SETC, STOP NUMBER 8 19 7 9 8 8 8
Total 67
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SM8521
Table 2 Addressing Mode Summary NAME Implied Register Register pair Register file Register file pair Register indirect Register indirect auto increment Register indirect auto decrement Register index Register pair indirect Register pair indirect r rr R RR @r (r)+ -(r) n(r)2 @rr (rr)+ -(rr) nn(rr)3 @nn(r)2 IM IML b p RA DA DAs DAp @DA PC - 128 to PC + 127 DA = 0000H-FFFFH DAs = 1000H-1FFFH DAp = FF00H-FFFFH DA = 0000H-FFFFH r = R0-R7 r = RR0, RR2, ... , RR14 R = 0 to 255 (R0-R15) R = 0, 2, ... 254 (RR0, RR2, ... , RR14) r = R0-R7 r = R0-R7 r = R0-R7 n = 00H-FFH, r = R1-R7 rr = RR0, RR2, ... , RR14 rr = RR0, RR2, ... , RR14 rr = RR0, RR2, ... , RR14 nn = 0000H-FFFFH rr = RR2, RR4, ... , RR14 nn = 0000H-FFFFH r = R1-R7 IM = 00H-FFH IML = 0000H-FFFFH b = 0 to 7 SYMBOL Range Operand 1
To specify the carry(C) and interrupt enable (I) in the instruction code.
General register [byte] General register [word] Register file (0000H-007FH) and (0080H-00FFH) [byte] Register file (0000H-007FH) and (0080H-00FFH) [byte] Memory (0000H-00FFH) [byte] Memory (0000H-00FFH) [byte] Memory (0000H-00FFH) [byte] Memory (0000H-00FFH) [byte] Memory (0000H-FFFFH) [word/byte] Memory (0000H-FFFFH) [word/byte] Memory (0000H-FFFFH) [word/byte] Memory (0000H-FFFFH) [word/byte] Memory (0000H-FFFFH) [word] The immediate data in the instruction code [byte] The immediate data in the instruction code [word] Register file (0000H-007FH) and memory (0080H-00FFH, FF00H-FFFFH) [bit] (1 bit of 1 byte pointed by R, n(r) and DAp) Register file (0010H-0017H) [byte] Program memory (1000H-FFFFH) Memory (0000H-FFFFH) [byte] Program memory (1000H-1FFFH) Program memory (FF00H-FFFFH) [byte] Memory (0000H-FFFFH)
auto increment
Register pair indirect auto decrement Register pair index Index indirect Immediate Immediate long Bit Port Relative Direct Direct short Direct special page Direct indirect
1 The data indicated by [ 2 R0 can not be used. 3 RR0 can not be used.
] is the unit of possible to use in Load and Arithmetic Instructions.
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SM8521
Register Lineup
Fig. 1 shows the SM85CPU register lineup. The CPU internal register consists of eight 8-bit general purpose registers (R0-R7), four 16-bit general purpose registers
7 RR0 RR2 RR4 RR6 15 RR8 RR10 RR12 RR14 R8 R10 R12 R14 7 PS0 7 PS1 7 SYS 7 SPH 15 PC 07 SPL 0 0 0 0 R9 R11 R13 R15 0 R0 R2 R4 R6 07 R1 R3 R5 R7 0
(RR8-RR14), a program counter (PC) and four other control registers. (The R0-R7 can be also used as four 16-bit general purpose registers (RR8-RR14).)
0
Fig. 1 Register Lineup
GENERAL PURPOSE REGISTER The eight 8-bit general purpose registers R0-R7 and all eight 16-bit general purpose registers (RR0RR14) are available for use as accumulator, index register and pointer registers. (The R0 and RR0 cannot be used as index register) The other eight 8-bit registers R8-R15 cannot be used as 8-bit general purpose register and as member of the register file. (about register file, refer to "Address Space.") The feature of the SM85CPU architecture is that general purpose registers are virtually allocated at 16-byte internal RAM. Actually, if the CPU accesses general purpose registers, the designated RAM will be accessed by the 5-bit register pointer (RP)V. When RP = 00000B, the registers occupy the first
16 bytes starting at 0000H. Incrementing the field, RP = 00001B, shifts the mapping by eight bytes so that the registers start at 0008H. As a result, the general purpose registers can be switched in 8-byte unit to any RAM location within 0000H-00FFH. Although the general purpose registers are members of the register file, which stores the data onto actual RAM, is different from the other members (control registers). That is, general purpose registers can be referred as registers, as register file (allocated at 0000H-000FH) and as RAM accessing by all addressing modes.
About register pointer (RP), refer to "Processor status 0 (PS0)".
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SM8521
CPU CONTROL REGISTER The SM85CPU has the following control register : processor status PS0, processor status PS1, system configuration register SYS, stack pointer SPH, SPL and program counter PC. All control register except the program counter PC are members of the register file and accessible by the register file R and the register file pair RR addressing modes. Processor status 0 (PS0) The processor status PS0 is an 8-bit readable/ writable register containing 2 fields, the upper 5-bit is register pointer (RP) and the lower 3-bit is interrupt mask. Bit 7
PR4 PR3 PR2 PR1 PR0 IM2 IM1
Bits 2 to 0 : Interrupt mask bits (IM)
BIT 000 001 010 011 100 101 111 111 CONTENT All maskable interrupts recognized Maskable interrupts with level 1 to 12 recognized Maskable interrupts with level 1 to 10 recognized Maskable interrupts with level 1 to 8 recognized Maskable interrupts with level 1 to 6 recognized Maskable interrupts with level 1 tto 4 recognized Maskable interrupts with level 1 to 2 recognized
0
IM0
Bits 7 to 3 : Register pointer (RP) This gives, in 8 bytes unit, the starting address in RAM for general purpose registers.
Address Low R0 R1
PS0
RP
IM R14 R15
Ex.) If RP = 00000B, general purpose registers will be virtually allocated at internal RAM 0000H-000FH. If RP = 00001B, general purpose registers will be virtually allocated at internal RAM 0008H-0017H.
High Internal RAM
Fig. 2 Register Pointer (RP) Setting Example
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SM8521
Processor status 1 (PS1) The processor status PS1 is an 8-bit readable/ writable register and consists of eight flag bits. These flags can be used as the condition codes for the conditional branch instructions. When CPU generates an interrupt, the content of processor status PS1 and the value of program counter PC automatically are pushed onto stack. Bit 7
C Z S V D H B I
Bit 7 : Sets '0' Bit 6 : Stack pointer configuration (SPC)
BIT 0 1 CONTENT 8-bit (SPL only) 16-bit (both SPL, SPH)
Bits 5 to 3 : Set '0' Bits 2 to 0 : Memory configuration (MCNF2-0)
BIT 000 110 Other combination CONTENT External memory expansion disable. External memory expansion mode (64 k bytesV) Do not use.
0
Bit 7 : Carry (C) It indicates that generated a carry in operation. Bit 6 : Zero (Z) It indicates that the operation result is zero. Bit 5 : Sign (S) It indicates that the operation result is negative (Sign bit = `1'). Bit 4 : Overflow (V) Executes the operation with the signed value. If the operation result cannot indicate complement on two, then the bit will be `1'. Bit 3 : Decimal adjustment (D) It indicates that the last arithmetic operation is a subtraction. Bit 2 : Half carry (H) It indicates that generated a carry between bit 3 and 4. Bit 1 : Bit (B) It indicates that the result of the last bit manipulation. Bit 0 : Interrupt enable (I) This is a flag which enables /disables all maskable interrupt. System configuration register (SYS) The system configuration register SYS is an 8-bit readable/writable register which sets the external memory expansion modes and selects 8-bit/16-bit stack pointer. Bit 7
SPC -
: In ROM space (60 k bytes), the field beyond the internal ROM is the external memory access field.
Stack pointer (SPL, SPH) The stack pointer SPL, SPH are 8-bit readable/ writable register and show the stack address. The bit SPC of the system configuration (SYS) specifies whether the stack pointer is 8 (SPL only) or 16 (both SPL and SPH) bits long. Program counter (PC) The program counter (PC) is a pointer for program memory and contains the starting address for the next instruction. Bit 15 0
The program counter PC is initialized to 1020H after hardware reset. That is, the application program starts executing from the address 1020H after hardware reset.
0
MCNF2 MCNF1 MCNF0
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SM8521
Address Space
The SM85CPU has a 64 k-byte address space, which is divided into RAM (0000H-0FFFH) and ROM (1000H-FFFFH) areas. The address 0000H-007FH are both shared by RAM and register file. Fig. 9-1 shows the SM8521 Memory Map. The RAM and register file allocated at 0000H-007FH can be selected by the addressing mode designated by instructions. The SM8521 supports an Memory Management Unit used to external memory area expantion. Refer to "Memory Management Unit (MMU)".
Register File Area
The register file is allocated between 0000H and 007FH. The first 16 bytes (0000H-000FH) area are general registers. The remainder is for CPU control registers, peripherals control register and data register.
RAM Area
The RAM area starts at the beginning 0000H of the address space. It overlaps the register file for the address 0000H-007FH. This arrangement is to shorten the instruction length as much as possible and to permit the use with both RAM and the register file for faster execution.
ROM Area
ROM area starts at the address 1000H of the space address. The first portion (1000H-101FH) is reserved for the interrupt vector table. Each 2 bytes entry in the vector table contains the address of interrupts. When an interrupt encountered, the CPU jumps to the corresponding branch address of vector table for program executing. The address 1020H marks the start of the user program area itself. Executing always starts at 1020H after hardware reset.
Data Type Bit Byte
Register file address 0000H-00FFH 0000H-00FFH
Memory address 0000H-00FFH or FF00H-FFFFH 0000H-00FFH 0000H-00FFH or FF00H-FFFFH (Under shorthand)
7 7 6 5
Data Format
0 4 3 2 1 0
Address Low
MSB
LSB
Word
Even byte, 0000H-00FEH, following byte (odd byte)
0000H-FFFEH following byte
MSB
Upper 8-bit Lower 8-bit LSB
BCD
0000H-00FFH
0000H-00FFH
Upper BCD digit
Lower BCD digit High
Fig. 3 Register File/Memory Data Formats
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SM8521
Data Format
The SM85CPU supports four data types : bit, 4-bit BCD, byte, and word data. REGISTER FILE DATA FORMATS The register file (0000H-007FH) and RAM (0080H00FFH) accessible with register file R and register file pair RR addressing support processing for all 4 data types : bit, 4-bit BCD, byte, and word data. Fig. 3 shows the data layout in the register file. * Bit data (register file) Bit manipulation instructions access bit data in the register by register file R addressing, which gives the byte address in the register file (0000H-007FH), or RAM (0080H-00FFH), and the operand b, which gives the bit number within the byte. * Byte data (register file) Instructions access the byte data in the register file by register file R addressing, which gives the byte data address in the register file (0000H-007FH) or RAM (0080H-00FFH). * Word data (register file) Instructions access word data in the register file by register file pair RR addressing, which gives the word address, even and 2 bytes address, in the register file (0000H-007FH) or RAM (0080H-00FFH). The address must be even (0, 2, 4,..., 254). Specifying an odd address leads to unreliable results. * BCD data (register file) The decimal adjust instruction (DA), used to adjust BCD digits after an odd or subtraction, accesses a BCD data byte in the register file by register file R addressing. * Notice for the general register on register file The general registers are the first 16 bytes (0000H000FH) in the register file. They can be accessed as byte-sized by register file R addressing and as word-sized by register file pair RR addressing. MEMORY DATA FORMATS The memory area (ROM and RAM 0000H-FFFFH) supports processing for all 4 data types : bit, 4-bit BCD, byte and word data. However, bit data is limited to the ranges (0000H-00FFH, FF00H-FFFFH), and 4-bit BCD data to the ranges 0000H-00FFH. Fig. 3 shows the data layout in memory. * Bit data (memory) Bit manipulation instructions access bit data in memory by register index n(r) addressing, which gives the byte address in the range (0000H-00FFH), or by direct special page DAp addressing, which gives the byte address in the range (FF00H-FFFFH), and the operand b, which gives the bit number within the byte. * Byte data (memory) Instructions access the byte data in memory by shorthand (0000H-00FFH or FF00H-FFFFH) or full (0000H-FFFFH) address. * Word data (memory) Instructions access the word data, continue 2 bytes, in memory by shorthand (0000H-00FFH or FF00H-FFFFH) or full (0000H-FFFFH) address. Unlike word data in the register file, the address can be even or odd. * BCD data (memory) The decimal adjust instruction (DA), used to adjust BCD digits after an odd or subtraction, accesses a BCD data byte in memory by register index @r addressing. * Notice for general register on memory The general registers are actually in a RAM area specified by register pointer RP, so they can be read and modify directly as RAM. While programming, the programmer must take care to arrange program data so that other RAM operations do not destroy general registers content.
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SM8521
Bus Timing
The SM85CPU is variable for system clock. The bit FCPUS2-FCPUS0 (bits 5 to 3 : CKKC) of the clock changing register CKKC can select system clock to 1/2, 1/4, 1/8, 1/16 and 1/32 of the main clock and 1/2 of sub-clock. The CPU operates at 1/32 clock of the main clock after hardware reset. INTERNAL MEMORY ACCESS TIMING The read cycle of internal RAM is 2 cycles. The internal RAM supports 2 cycles for reading or writing. EXTERNAL MEMORY ACCESS TIMING The external memory supports 2 cycles for reading or writing. Fig. 5 shows the read timing and Fig. 6 shows the write timing. INSTRUCTION PREFETCH The SM85CPU, which execution cycle overlaps with the OP code, fetches next instruction OP code during one instruction execution cycle. For example, the execution time for 2 bytes instructions (MOV R, r) of transferring the RAM contents to a register is 4 cycles.
Internal clock
Pre-instruction
Executing preinstruction OP code fetch Operand fetch RAM read Register write
Transfer instruction
Next instruction Fetch cycle Execution time
OP code fetch Execution cycle
Fig. 4 Instruction Execution for Transfer Instruction (2 Bytes)
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SM8521
* External memory access timing (read timing)
A0-A20
tRSA
RDB
tRSD tWRD
tRHA
tRHD
D0-D7
Valid data
tRSA : The time between address firm and RDB signal falling Low level firm. tRSD : The time between RDB signal firm and input valid data firm. tWRD : RDB signal Low level width.
tRHA : The time between RDB signal rising High level firm and address change. tRHD : The time between RDB signal rising High level firm and output data floating. Load capacitance is 50 pF.
Fig. 5 External Memory Access Timing (Read Timing)
Operating condition
PARAMETER Address setup time Read data setup time RDB signal pulse width Address hold time Read data hold time SYMBOL tRSA tRSD tWRD tRHA tRHD tSYS - 50 0 0 MIN. TYP. tSYS
(VDD = 4.5 to 5.5 V, TOPR = -10 to 60C) MAX. UNIT NOTE
tSYS + 50 tSYS/2 - 30 tSYS ns ns ns ns ns 1 1 1
NOTE :
1. tSYS : The system clock period (main clock x 1/2) when the low order 3 bits in the clock change register FCPUS2-FCPUS0 are 100B.
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SM8521
* External memory access timing (write timing)
A0-A20
tWSA
WRB
tWHA tWWR tWSD
D0-D7
Invalid data
Valid data
tWHD
tWSA : The time between address firm and WRB signal falling Low level firm. tWSD : The time between WRB signal rising High level firm and output valid data firm. tWWR : WRB signal Low level width. tWHA : The time between WRB signal rising High level firm and address change. tWHD : The time between WRB signal rising High level firm and output data floating. Load capacitance is 50 pF.
Fig. 6 External Memory Access Timing (Write Timing)
Operating condition
PARAMETER Address setup time Data setup time WRB signal pulse width Address hold time Data hold time SYMBOL tWSA tWSD tWWR tWHA tWHD tSYS - 50 tSYS - 60 10 10 MIN. TYP.
(VDD = 4.5 to 5.5 V, TOPR = -10 to 60C)
MAX. tSYS + 50 UNIT NOTE 1 1 1
tSYS
tSYS + 30
tSYS
ns ns ns ns ns
NOTE :
1. tSYS : The system clock period (main clock x 1/2) when the low order 3 bits in the clock change register FCPUS2-FCPUS0 are 100B.
- 17 -
SM8521
SYSTEM CONTROL Oscillator Circuit
The SM8521 is built-in the main-clock and subclock oscillator circuits for generating clock signal. The main-clock oscillator circuit is applied to 1.5 to 10 MHz. The sub-clock oscillator circuit is applied to 32.768 kHz.
Clock System
The SM8521 uses the main-clock and sub-clock oscillator circuits to generate the required clock.
fCK = 11.0592 MHz CKIN CKOUT Main-clock generator circuit fCK 1/2
The system clock, leads CPU operation, is one of the five clocks which divides the main-clock (fCK) into 1/2, 1/4, 1/8, 1/16 and 1/32. It also selects from sub-clock (f32K). In addition, the clocks supplied to the peripheral functions are fc1-fc10 divided by the prescaler PRS0 and derived from the 1/2 clock of main-clock (fCK/2), and fx1-fx8 divided by the prescaler PRS1 and derived from the subclock.
System clock frequency control
CG
System clock
SM85CPU
Warming up counter fc10
Prescaler PRS0 fCK/2 fc1-fc10
Function blocks operation
RAM register read/write
Interrupt control
Peripheral functions f32K OSCIN OSCOUT Sub-clock generator circuit
f32K = 32.768 kHz
f32K
Prescaler PRS1
Fig. 7 SM8521 Clock System
- 18 -
SM8521
System clock frequency control Main-clock fCK
1/2 1/2 1/2 1/2 1/2
fCK/2 fCK/2
CG Selector 5 f32K System clock fSYS
fCK/4
fCK/8 fCK/16 fCK/32
Prescaler PRS2 (frequency divider on fc10) Prescaler PRS0 (frequency divider on fCK/2)
1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
fc12 fc13 fc14 fc15
For warming up counter
fc10 fc11 fc12 fc13 fc14 fc15 fc16
Warming up counter (frequency divider on fc10)
1/2 1/2 1/2 1/2 1/2 1/2 1/2
Prescaler PRS1 (frequency divider on f32K) f32K Sub-clock fx1 fx2 fx3 fx4 fx5 fx6 fx7 fx8
1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
8 8
To function blocks
Fig. 8 SM8521 Clock System (Equivalent Circuit for Clock System Peripheral Blocks)
Clock change register (CKKC) Clock change register CKKC is an 8-bit readable/ writable register containing the control of system clock change and the setting of warming up period after waking up from the STOP mode. Clock change register CKKC is initialized to 00H after hardware reset. Bit 7
FCPUEN MCKSTP FCPUS2 FCPUS1 FCPUS0 TFCPU
Bits 5 to 3 : System clock selection bits (FCPUS2-FCPUS0) Under the bit FCPUEN = `1', if executes the STOP instruction, the bits will be valid.
BIT 000 001 010 011 100 101, 110 111 SYSTEM CLOCK FREQUENCY System clock = (1/32) x main-clock System clock = (1/16) x main-clock System clock = (1/8) x main-clock System clock = (1/4) x main-clock System clock = (1/2) x main-clock Reserved System clock = (1/2) x sub-clock
0
WUPS1 WUPS0
Bit 7 : Clock change enable bit (FCPUEN)
BIT 0 1 CONTENT Disables system clock speed change Enables system clock speed change
Bit 6 : Main-clock stopped bit (MCKSTP) Main-clock stopped allows switching to sub-clock used as system clock.
BIT 0 1 CONTENT Main-clock operation Main-clock stop
Bit 2 : Reserved bit (TFCPU) Always write `0' to this position. Writing a `1' produces unrealiable operation. Bits 1 to 0 : Warming up selection bits (WUPS1-WUPS10) The bits are able to set the warming up period of after wake up from STOP mode.
WARMING UP PERIOD AFTER STOP BIT 00 01 10 11 MODE RELEASES (when main-clock (fCK) = 10 MHz) 218 x main-clock period (26.21 ms) 217 x main-clock period (13.10 ms) 216 x main-clock period (6.553 ms) 215 x main-clock period (3.276 ms)
- 19 -
Address Space 0000H General register 0001H General register R0 R1 R15 Register File 000FH General register 0010H Control register -
Memory Map
0000H Register file physically present Area
007FH 0080H
RAM physically present Area
Fig.9 shows the SM8521 memory map.
03FFH 0400H Reserved Area Stack Pointer Stack Pointer Processor Status 0 Processor Status 1 SPH SPL PS0 PS1
1 2 Interrupt vector area External Internal ROM ROM Control register External ROM External ROM Timer 0 (TIM 0) Reserved External Interrupt (EXTINT) UART transmit/receive completion (UART) Reserved Reserved LCD controler (LCDC) DMA (DMA) 007FH
0FFFH 1000H 101FH 1020H 1FFFH 2000H
0018H 0019H 001AH 001BH 001CH 001DH 001EH 001FH 0020H System Configuration Register SYS CKC Clock change register Reserved
Fig. 9-1 SM8521 Memory Map (1)
- 20 Reserved area
3FFFH 4000H
Reserved Timer 1 (TIM 1) Reserved Clock (CK) Reserved Input/output port (PIO) Watchdog timer (WDTINT) NMI, illegal instrtuction (NMI, ILL)
ROM physically present Area
5FFFH 6000H
7FFFH 8000H
9FFFH A000H
DFFFH E000H
FFFFH
1000H 1001H Interrupt Vector 1002H External 1003H ROM 1004H 1005H External 1006H ROM 1007H 1008H 3 1009H VRAM 100AH 100BH Extend I/O 100CH Extend RAM 100DH 1 ROM disable (In case of MMU0 is set.) 100EH 2 ROM enable (At reset) 100FH 3 Write only during CPU access
(Upper) (Lower) (Upper) (Lower) (Upper) (Lower) (Upper) (Lower) (Upper) (Lower) (Upper) (Lower) (Upper) (Lower) (Upper) (Lower)
1010H 1011H 1012H 1013H 1014H 1015H 1016H 1017H 1018H 1019H 101AH 101BH 101CH 101DH 101EH 101FH
(Upper) (Lower) (Upper) (Lower) (Upper) (Lower) (Upper) (Lower) (Upper) (Lower) (Upper) (Lower) (Upper) (Lower) (Upper) (Lower)
SM8521
Address Register name R/W Initial value
RR0 RR2 RR4 RR6 RR8 RR10 RR12 RR14 IE0 IE1 IR0 IR1 P0 P1 P2 P3 SYS CKC
Register name
R/W Initial value Address
0000H
Fig. 9-2 SM8521 Memory Map (2)
- 21 SP PS0 PS1
0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH 001DH 001EH 001FH
General purpose register R0 General purpose register R1 General purpose register R2 General purpose register R3 General purpose register R4 General purpose register R5 General purpose register R6 General purpose register R7 General purpose register R8 General purpose register R9 General purpose register R10 General purpose register R11 General purpose register R12 General purpose register R13 General purpose register R14 General purpose register R15 Interrupt enable register 0 Interrupt enable register 1 Interrupt request register 0 Interrupt request register 1 PIO data register 0 PIO data register 1 PIO data register 2 PIO data register 3 Reserved System configuration register Clock change register Reserved Stack pointer H SPH Stack pointer L SPL Processor status register 0 Processor status register 1 0020H 0021H 0022H 0023H 0024H 0025H 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 00H 00H 00H 00H 00H 00H 00H 00H 0000000 00H Undefined Undefined Undefined 0
003FH
PIO control register 0 P0C R/W PIO control register 1 P1C R/W PIO control register 2 P2C R/W PIO control register 3 P3C R/W MMU data register 0 MMU0 R/W MMU data register 1 MMU1 R/W MMU data register 2 MMU2 R/W MMU data register 3 MMU3 R/W MMU data register 4 MMU4 R/W Reseved Reseved UART Transmit data register URTT W UART Receive data register URTR R UART Status register URTS R UART Control register URTC R/W Reseved Control/Status register LCC R/W Display H-timing register LCH R/W Display V-timing register LCV R/W *1 Reserved Controler register DMC R/W Source X-coordinate register DMX-1 R/W Source Y-coordinate register DMY-1 R/W X-width register DMDX R/W Y-width register DMDY R/W Destination X-coordinate register DMX2 R/W Destination Y-coordinate register DMY2 R/W Pallet register DMPL R/W ROM bank register DMBR R/W VRAM page register DMVP R/W Reserved Reserved -
00H 00H 00H 00H 00H 00H 00H 00H 00H FFH 00H 0000010 00H 00H 000000 0000000 0000000 00H 00H 00H 00H 00H 00H 00H 0000000 00 -
NOTES : * R/W indicates that there is at least one bit in the register is capable of read/write.
(The register indicated by R/W includes the bit of special-purpose register for read). R indicates that the register is only for read.
SM8521
* indicates that the corresponding bit is undefined.
*1 The most significant bit is read only.
Fig. 9-3 SM8521 Memory Map (3)
- 22 R R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R/W R/W R/W
Address 0040H 0041H 0042H 0043H 0044H 0045H 0046H 0047H 0048H 0049H 004AH 004BH 004CH 004DH 004EH 004FH 0050H 0051H 0052H 0053H 0054H 0055H 0056H 0057H 0058H 0059H 005AH 005BH 005CH 005DH 005EH 005FH
Register name SG control register SGC Rserved SG0 output level control register SG0L Rserved SG1 output level control register SG1L Rserved SG0 time constant register (High) SG0TH SG0 time constant register (Low) SG0TL SG1 time constant register (High) SG1TH SG1 time constant register (Low) SG1TL SG2 output level control register SG2L Rserved SG2 time constant register (High) SG2TH SG2 time constant register (Low) SG2TL SG-D/A direct output register SGDA Rserved Timer control register 0 TM0C Timer data register 0 TM0D Timer control register 1 TM1C Timer data register 1 TM1D Clock timer CLKT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Watchdog timer register WDT Watchdog timer control register WDTC
*1
Initial 00000 00000 00000 0000 00H 0000 00H 00000 0000 00H 00H 0000 00H 00000 00H 00H 00H 38H SG0W0 SG0W1 SG0W2 SG0W3 SG0W4 SG0W5 SG0W6 SG0W7 SG0W8 SG0W9 SG0W10 SG0W11 SG0W12 SG0W13 SG0W14 SG0W15 SG1W0 SG1W1 SG1W2 SG1W3 SG1W4 SG1W5 SG1W6 SG1W7 SG1W8 SG1W9 SG1W10 SG1W11 SG1W12 SG1W13 SG1W14 SG1W15
Address 0060H 0061H 0062H 0063H 0064H 0065H 0066H 0067H 0068H 0069H 006AH 006BH 006CH 006DH 006EH 006FH 0070H 0071H 0072H 0073H 0074H 0075H 0076H 0077H 0078H 0079H 007AH 007BH 007CH 007DH 007EH 007FH
Register name SG0 waveform register 0 SG0 waveform register 1 SG0 waveform register 2 SG0 waveform register 3 SG0 waveform register 4 SG0 waveform register 5 SG0 waveform register 6 SG0 waveform register 7 SG0 waveform register 8 SG0 waveform register 9 SG0 waveform register 10 SG0 waveform register 11 SG0 waveform register 12 SG0 waveform register 13 SG0 waveform register 14 SG0 waveform register 15 SG1 waveform register 0 SG1 waveform register 1 SG1 waveform register 2 SG1 waveform register 3 SG1 waveform register 4 SG1 waveform register 5 SG1 waveform register 6 SG1 waveform register 7 SG1 waveform register 8 SG1 waveform register 9 SG1 waveform register 10 SG1 waveform register 11 SG1 waveform register 12 SG1 waveform register 13 SG1 waveform register 14 SG1 waveform register 15
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
NOTES : * R/W indicates that there is at least one bit in the register which is capable of read/write.
(The register indicated by R/W includes the bit of special-purpose register for read). R indicates that the register is only for read.
SM8521
* indicates that the corresponding bit is undefined.
*1 Bits 0 to 5 are read only. Bits 6 and 7 are read/write.
SM8521
Hardware Reset
The hardware reset is an initial function for SM8521 system and comes from the following sources. * External reset If the RESETB pin is applied to Low level in SM8521 operating, the hardware resets. * Watchdog timer overflow While watchdog timer overflows, the hardware resets. The above 2 hardware reset sources initializate the system. OPERATING EXPLANATIONS * Hardware reset operation When the SM8521 is operating, a built-in pull-up resistor keeps the RESETB pin at High level. If external circuit (like as reset IC etc.) applies Low level voltage to RESETB pin, the SM8521 is reset by hardware after approximately two instruction cycles. To ensure hardware reset execution keeps the RESETB pin at Low level over two instruction cycles of system clock. The pin back to High level from Low level starts the warming up counter built-in SM8521. When the counter overflows, about 218 x main-clock leaves its hardware reset state and begins the program execution from the instruction at address 1020H. In the warming up interval, SM8521 is in HALT mode state. Same as watchdog timer overflow case, the CPU leaves the hardware reset behind warming up period.
Interrupt Function
The SM8521 supports 10 interrupt sources. In these interrupts, watchdog timer and illegal instruction trap interrupts belong to non-maskable interrupts, the others, however, are maskable interrupts. 10 interrupt sources are shared to independent interrupt vector respectively, in the ROM address area between 1000H-101FH. And, the maskable interrupts are set 8 steps with priority level.
210
Interrupt request register IR0 IR1 IE0 IE1
PS0 Interrupt enable register PS1
IM
0
I
With priority 8 levels Interrupt mask processor Interrupt request latch Maskable interrupt
With priority 1 level Interrupt signal WDT (NMI)
Priority selector
Illegal instruction trap
Interrupt process
Fig. 10 Interrupt Block Diagram
- 23 -
SM8521
Table 3 SM8521 Interrupt Vectors Location and Their Priority VECTOR LOCATION 1000H 1002H 1006H 1008H 100EH 1012H 1016H 101AH 101CH INTERRUPT SOURCE DMA Timer 0 External interrupt UART transmit/receive complete LCD controller Timer 1 Clock Input/output port Watchdog timer overflow SYMBOL DMAINT TIM0INT EXTINT UARTINT LCDCINT TIM1INT CKINT PIOINT WDTINT PRIORITY 1 2 3 4 5 6 7 8 -
101EH NMI, illegal instruction NMIINT, ILLINT - The priority levels determine the order in which the chip process simultaneous interrupts. It also denotes the priority level of
mask interrupts by setting the bits IM2-IM0 (bits 2-0 : PS0).
REGISTER EXPLANATIONS PS0 (Interrupt maskbit (IM) of processor status 0) The bits IM2-IM0 can set the acceptable level for interrupt. The maskable interrupt requested by CPU is set 1 to 8 priority levels. These bits IM2-IM0 determine processing interrupts which priority levels.
Bits 2 to 0 : Interrupt mask bits (IM2-IM0)
BIT 000 001 010 011 100 101 110 111 CONTENT All maskable interrupts recognized. All maskable interrupts recognized. Maskable interrupts with 1 to 7 level recognized. Maskable interrupts with 1 to 6 level recognized. Maskable interrupts with 1 to 5 level recognized. Maskable interrupts with 1 to 4 level recognized. Maskable interrupts with 1 to 3 level recognized. Maskable interrupts with 1 to 2 level recognized.
NOTE :
When an interrupt enables by interrupt mask bit, if all interrupt conditions are setup, then the CPU starts to the interrupt processing.
- 24 -
SM8521
PS1 (Interrupt enable bit (I) of processor status 1) The bit I (bit 0 : PS1) enables/disables all maskable interrupts. After hardware reset, the bit I is set `0' and so all maskable interrupts are in disable state. Bit 0 : Interrupt enable (I)
BIT 0 CONTENT Disables to accept all maskable interrupts Enables to accept maskable interrupt. For 1 each maskable interrupt can be enabled/ disabled by interrupt enable register IE0, IE1 and bits IM2-IM0.
IE1 (Interrupt enable register 1) The interrupt enable register IE1 is an 8-bit readable/writable register containing the settings for enable/disable to accept interrupt sources. Bit 7
TIM1 CLK PIO -
0
Except that write to processor status PS1 directly, the bit I can be set/cleared by the following specialpurpose instructions. (Under normal case, the special-purpose instructions are used.) DI instruction : bit I is set `0'. EI instruction : bit I is set `1'. IE0 (Interrupt enable register 0) The interrupt enable register IE0 is an 8-bit readable/writable register containing the settings for enable/disable to accept interrupt sources. Bit 7
DMA TIM0 EXTINT UART -
Bit 7 : Sets `0'. Bit 6 : Timer 1 interrupt enable bit Bit 5 : Sets `0'. Bit 4 : Clock interrupt enable bit Bit 3 : Sets `0'. Bit 2 : PIO interrupt enable bit Bits 1 to 0 : Set `0'.
BIT 0 1 Disable Enable CONTENT
0
LCDC
The interrupt enable register IE0 and IE1 are also used to wake up the chip from standby mode (STOP mode, HALT mode) by setting the interrupt to enable. If the interrupt enabled by the interrupt enable register IE0 and IE1 occurs, the chip will wake up from standby mode. But also there are interrupt sources which cannot use to wake up from STOP mode. For more details, refer to "Stand by Function".
Bit 7 : DMA interrupt enable bit Bit 6 : Timer 0 interrupt enable bit Bit 5 : Sets `0'. Bit 4 : External interrupt enable bit Bit 3 : UART interrupt enable bit Bits 2 to 1 : Set `0'. Bit 0 : LCD cotroller interrupt enable bit
BIT 0 1 Disable Enable CONTENT
- 25 -
SM8521
IR0 (Interrupt request register 0) The interrupt request register IR0 is an 8-bit readable/writable register containing the setting for enable/disable to accept interrupt sources. Bit 7
DMA TIM0 EXT UART -
0
LCDC
Bit Bit Bit Bit Bit Bit Bit Bit
7 6 5 4 3 2 1 0
0 1
: : : : : : : :
DMA interrupt request bit Timer 0 interrupt request bit Sets `0'. External interrupt request bit UART interrupt request bit Sets `0'. Sets `0'. LCD controller Interrupt Request bit
CONTENT Disable Enable
The interrupt request register IR0 and IR1 are also used to wake up the chip from standby mode (STOP mode, HALT mode) by setting the interrupt to enable. If the interrupt enabled by the interrupt request register IR0 and IR1 occurs, the chip will wake up from standby mode. But also there are interrupt sources which cannot use to wake up from STOP mode. For more details, refer to "Standby Function".
BIT
IR1 (Interrupt request register 1) The interrupt request register IR1 is an 8-bit readable/writable register containing the setting for enable/disable to accept interrupt sources. Bit 7
TIM1 CLK PIO -
0
Bit Bit Bit Bit Bit Bit Bit
7 6 5 4 3 2 1
0 1
: Sets `0'. : Timer 1 interrupt request bit : Sets `0'. : Clock interrupt request bit : Sets `0'. : PIO interrupt request bit to 0 : Set `0'.
CONTENT Disable Enable
BIT
- 26 -
SM8521
Standby Function
The standby function is a function which temporarily stops program execution so as to conserve power. The standby mode is when the chip enters temporary stop state from the operating state, executing program. It contains both STOP and HALT modes, either of which can be selected according to your desires. If the CPU executes the STOP mode or HALT mode, the chip will switch to standby mode from an operating mode. If the wake up source of the standby mode encounters an interrupt the chip returns to operating mode from the standby mode. Fig. 11 shows its state transition diagram.
External reset request
Warming up end Hardware Reset HALT Mode
Internal/external reset request
HALT instruction execution
STOP mode wake up source
HALT mode wake up source
Normal Operation STOP instruction execution
STOP Mode
Operating Mode
Standby Mode
NOTE : When the chip wakes up from STOP mode, it returns to operating mode behind warming up period.
Fig. 11 State Transition Diagram
NOTE :
The STOP instruction is also used for clock change function, which its operation is different from switching the chip to STOP mode, take care to use it.
- 27 -
SM8521
Table 4 System State at Standby Mode Transition method Wake up method CPU Main-clock Sub-clock RAM, register I/O port Function blocks Timer Capture trigger UART LCDC Waveform generator
1 The interrupts used to wake up the chip from STOP mode only have the external interrupts and the internal interrupts generated by operatable Timer, and SIO.
HALT MODE HALT instruction execution Hardware reset, interrupt Stop Operating Operating Remain2 Remain (interruptable) Operating Operating Operating Operating Operating
STOP MODE STOP instruction execution Hardware reset, interrupt1 Stop Stop Operating Remain2 Remain (interruptable) The timer used main-clock as counter clock is stop. It used external clock as counter clock can still operate. Stop Stop Stop Stop
2 General registers, control registers, and the other memory content all are remained. But something will be changed for the operatable blocks at STOP mode (for example, interrupt flag register IR0, IR1 content, etc.)
ABOUT HOU TO USE HALT MODE AND STOP MODE The chip switches back to the operating mode from the HALT mode immediately after the wake up sources are encountered. For this reason, the HALT mode is more suitable for systems that need to be immediately woke up frequently. And, all interrupt sources (other than illegal instruction trap) can wake up the chip from the HALT mode. Switching back to the operating mode from the STOP mode after the wake up sources are encountered must pass a warming up period. In addition, the function blocks used by the main-clock cannot be used in the wake up from STOP mode. Since the sampling circuit is stopped, it can not accept the PINT0 input, either.
For this reason, the STOP mode (conserving more power than the HALT mode) is suitable for systems that can easily support the longer time that it will take to get, back to the operating mode (warming up period) . In standby mode, I/O ports setting and output level for output ports are remained. Before switches to standby mode, in order to reduce to the current through every pins, set with program.
- 28 -
SM8521
I/O PORTS
The SM8521 supports four 8-bit I/O ports. Each port can be selected one out of input, outpit, input with built-in pull-up resistor and open-drain in each 2-bit.
Internal Bus
Data register
I/O control circuit Input/output pins
Control register
Fig. 12 PIO Block Diagram
P0 to P3 (PIO data register) Bit 7
PX7 PX6 PX5 PX4 PX3 PX2 PX1
Bits 3 to 2 : 0
PX0
BIT 00 01 10 11 Input
CONTENT Input (with pull-up resistor) Output Output (open-drain)
(x = 0, 1, 2, 3) NOTE :
In case of reading P0-P3 register on condition that control register is input state, data of those pins is read. In case of on condition that control register is output state, data of register is read.
Bits 1 to 0 :
BIT 00 01 10 11 CONTENT Input Input (with pull-up resistor) Output Output (open-drain)
P0C to P2C (PIO control register) Bit 7
0
PXC7 PXC6 PXC5 PXC4 PXC3 PXC2 PXC1 PXC0
(x = 0, 1, 2) Bits 7 to 6 :
BIT 00 01 10 11 Input Input (with pull-up resistor) Output Output (open-drain) CONTENT
Bits 5 to 4 :
BIT 00 01 10 11 CONTENT Input Input (with pull-up resistor) Output Output (open-drain)
- 29 -
SM8521
P3C (Control register) Bit 7
0
Bits 3 to 2 :
BIT 00 01 10 11 CONTENT Input Input (with pull-up resistor) Output Output (open-drain)
P3C7 P3C6 P3C5 P3C4 P3C3 P3C2 P3C1 P3C0
Bits 7 to 6 :
BIT 00 01 10 11 Input Input (with pull-up resistor) Output/(Timer 1 clock outputs through P37) Output/(Timer 1 clock outputs through P37) CONTENT
Bits 1 to 0 :
BIT 00 Input Input (with pull-up resistor) Output Output (open-drain) 01 CONTENT
Bits 5 to 4 :
BIT 00 01 10 11 CONTENT Input Input (with pull-up resistor) Output Output (open-drain)
10 11
TIMER/COUNTERS
The SM8521 supports 8-bit timer x 2, and clock timer x 1. One out of 8-bit prescaler output can be selected as an 8-bit timer input.
Internal bus
Control register
Data register Comparator Interrupt
fCK
8-bit prescaler
8-bit up-counter
Fig. 13 8-Bit Timer Block Diagram
- 30 -
SM8521
8-BIT TIMER REGISTER TM0C, TM1C (Control registers) Bit 7
0
TM0D, TM1D (Data register) Bit 7
0 (x = 0, 1)
TMXC7 TMXC6 TMXC5 TMXC4 TMXC3 TMXC2 TMXC1 TMXC0
TMXD7 TMXD6 TMXD5 TMXD4 TMXD3 TMXD2 TMXD1 TMXD0
(x = 0, 1) Bit 7 : Start/stop Bits 6 to 3 : Set `0' Bits 2 to 0 :
PRESCALER 000 001 010 011 100 101 110 111 INPUT CLOCK FOR 8-BIT UP-COUNTER fCK/2 fCK/1 024 fCK/2 048 fCK/4 096 fCK/8 192 fCK/16 384 fCK/32 768 fCK/65 536
Bits 7 to 0 : Content of counter (read), time constant (write) NOTES : * After reset, the status of both TM0C and TM1C becomes
0000B, and both TM0D and TM1D becomes 00000000B. * Every time between the value of 8-bit up counter and the value of time constant register coincide in timer execution, output signal inverts.
Clock Timer
Clock timer is for real time clock. Dividing sub-clock (32.768 kHz), 1 s or 1 min interrupt occurs.
1s 1 min Selector Interrupt
32.768 kHz
Prescaler
1/60 counter
Control register
Data bus NOTE : In case of run/reset bit is zero, both upper 8 bits in prescaler and all bits in 1/60 counter are reset.
Fig. 14 Clock Timer Block Diagram
- 31 -
SM8521
CLOCK TIMER REGISTER CLKT (Clock timer register) Bit 7
0
Bit 7 : Run/reset
BIT 0 1 Counter reset Run STATUS
WDTC (Watchdog timer control register) Watchdog timer control WDTC is an 8-bit read only register which sets watchdog timer to start/stop, counter clear designation, and selects the count clock. Bit 7
WDTST WDTRN
0
WDTCR WCNT2 WCNT1 WCNT0
Bit 6 : Minute/second
BIT 0 1 STATUS 1 second 1 minute
Bit 7 : Watchdog timer start/stop bit (WDTST)
BIT 0 1 CONTENT Timer stop [WDT is cleared.] Timer start
Bits 5 to 0 : Value of counter (read only)
Bit 6 : Operation select while watchdog timer overflow (WDTRN)
BIT 0 1 CONTENT Hardware reset Non-maskable interrupt
Watchdog Timer Register (WDT)
PRS2 (Prescaler 2) Prescaler PRS2 generates the count clock to watchdog timer counter WDT. The following conditions are to clear all bits of prescaler PRS2. * When hardware reset. * When watchdog timer counter WDT stopped. * When counter WDT is cleared by writing `1' to the bit WDTCR (bit 3 : WDTC). PRS2 fc2 1/2 1/2 1/2 1/2 1/2 fc11 fc12 fc13 fc14 fc15 Prescaler PRS2 divides the frequency derived from input clock fc10 (204.8 s : main-clock = 10 MHz), then fc11-fc15 are output. WDT (Watchdog timer counter register) Watchdog timer counter WDT is an 8-bit read only register which counts up from input clock.
Bits 5 to 4 : set `0'. Bit 3 : Counter clear bit (WDTCR) [write only bit]
BIT 0 1 CONTENT No clear Only in writing operation, WDT is cleared.
Bits 2 to 0 : Watchdog timer counter clock selection bits (WCNT2-WCNT0)
BIT 000 001 010 011 100 101 110 111 COUNT CLOCK fc12 (819 s1) fc13 (1.639 ms1) fc14 (3.278 ms1) fc15 (6.578 ms1) fx5 (0.976 ms2) fx6 (1.95 ms2) fx7 (3.90 ms2) fx8 (7.81 ms2)
1 The value in ( ) is the period when main-clock is 10 MHz. 2 The value in ( ) is the period when sub-clock is 32.768 kHz.
- 32 -
SM8521
LCDC/DMA
The SM8521 supports LCD controller (LCDC) to control LCD pannel, in a kind of dot matrix, which is required external LCD drivers. LCDC transfers display data in the external VRAM to the LCD driver. The SM8521 supports a DMA, which can transfer the data at the High speed, between ROM and VRAM, VRAM and VRAM, and external RAM and VRAM, without through the CPU. DMA transfers display data in the ROM and external RAM to VRAM.
External address bus ROM address generator
Internal bus
Source/destination register
Timing generator Shift register
Interrupt (CPU)
LCD driver
VRAM address generator Data composition circuit External data bus
VRAM
Fig. 15 LCD/DMA Block Diagram
- 33 -
SM8521
VRAM Configulation
VRAM configulation is shown below. VRAM, maximum 16 k bytes (160 x 200-dot x 2phase or 200 x 160-dot x 2-plane), can be accessed. LCD diaplays a phase specified. Address of VRAM0 and VRAM1 is A000H-BFFFH and C000H-DFFFH respectively. DMA transfers rectangle display data, in arbitrary size specified in ROM and external RAM, to VRAM. NOTE :
Do not write data directly to VRAM while transferring data to LCD driver (MSB of LCC register is 1 and V-blank flag is 0).
0 Bit 7 6 5 4 3 2 1 0
1
2
3
dot 0
dot 1
dot 2
dot 3
4-dot/byte
dot data = 00 color 0 01 color 1 10 color 2 11 color 3
160/200-dot
160/200-dot VRAM 160-dot x 200-dot x 2-plane = 16 k-byte
Fig. 16 VRAM Configuration
- 34 -
SM8521
DMA Transfer
* ROM to VRAM transfer mode
Y1
256-dot X1 DY
DX 256-dot
ROM
Y2
160/200-dot X2
VRAM 160/200-dot
Also, transfers between VRAMs. * VRAM to VRAM transfer mode
Y2 X1
Y1
DY 160/200-dot X2 DX
VRAM 160/200-dot
- 35 -
SM8521
Compound and Overwrite Mode
To transfer display data, DMA provides two modes. One is compound mode that source dot data zero is not stored into the destination. Second is
VRAM ROM
overwrite mode that any dot data is stored into the destination.
VRAM
+
VRAM dot data
ROM dot data
ROM dot data = 0 : Transparent
ROM and VRAM
Fig. 17 An Example of Transfer ROM to VRAM in Compound Mode
- 36 -
SM8521
Registers
LCDC/DMA registers are shown below. LCDC register is initialized at the system initialization. After setting each parameter, set the DMA start bit to `1' and execute HALT instruction, then DMA transfer starts. LCC (LCD control/status register) Bit 7
Bits 3 to 1 : LCDC/DMA clock bits
BIT 000 001 010 011 100 101 110 111 fCK/2 fCK/4 fCK/6 fCK/8 fCK/10 fCK/12 fCK/14 fCK/16 LCDC/DMA CLOCK
0
DISON DISPG GRAD1 GRAD0 LCCL2 LCCL1 LCCL0 NORWH
Bit 7 : Display ON/OFF
BIT 0 1 DISPLAY ON/OFF Display OFF Display ON
Bit 0 : Normal white bar bit
BIT 0 1 Normal white Normal black STATUS
Bit 6 : Display page A/B bit
BIT 0 1 DISPLAY PAGE Page A Page B
LCH (Display horizontal timing register) Bit 7 0
HD0T HTIM4 HTIM3 HTIM2 HTIM1 HTIM0
Bits 5 to 4 : Gradation control bits (Depth of black and white on real LCD)
BIT 00 01 10 11 0 Black 0 Black 0 Black GRADATION CHOOSEN 1 Gray 1 1 Gray 1 2 Gray 2 2 Gray 3 3 White 3 White
Bits 7 to 6 : Set `0'. Bit 5 : H-dot size bit
BIT 0 1 HORIZONTAL DOT SIZE 160 200
Reserved 1 Gray 2 2 Gray 3
Bits 4 to 0 : H-timing bits
3 White
NOTE : NOTE : Gray scale
White Gray3 Gray2 Gray1 Black V-blank width bit must not be filled with 0000B. Otherwise, LCDC interrupt can not be effective.
Horizontal display cycle = (shift clock x LCDC/DMA clock ) x (H-timing + 1) Shift clock = 40 (at H-dot size = 160), 50 (at H-dot size = 200) Frame cycle = Horizontal display cycle x (V-line size + V-blank width)
- 37 -
SM8521
LCV (Display vertical timing register) Bit 7
VBLNK VL1
0
DMC (DMA control register) Bit 7
DMST -
0
VL0 VBWD3 VBWD2 VBWD1 VBWD0
INDCY INDCX TRN1 TRN0 COOVr
Bit 7 : V-blank bit (read only)
BIT 0 1 STATUS Non-vertical blank period Vertical blank period
Bit 7 : DMA start bit
BIT 0 1 STATUS DMA stops DMA starts transfering data
Bit 6 : Sets `0'. Bits 5 to 4 : V-line size bits
BIT 00 01 10 100 160 200 VERTICAL LINE SIZE
Bits 6 to 5 : Set `0'. Bit 4 : Increment y/decrement y bit (Increment/decrement y-coordinate of source)
BIT 0 1 STATUS Increment y Decrement y
Bits 4 to 0 : V-blank width bits NOTE :
V-blank width bit must not be filled with 0000B. Otherwise, LCDC interrupt can not be effective.
Bit 3 : Increment x/decrement x bit (Increment/decrement x-coordinate of source)
BIT 0 1 Increment x Decrement x STATUS
Horizontal display cycle = (shift clock x LCDC/DMA clock ) x (H-timing + 1) Shift clock = 40 (at H-dot size = 160), 50 (at H-dot size = 200) Frame cycle = Horizontal display cycle x (V-line size + V-blank width)
Bits 2 to 1 : Transfer mode bits
BIT 00 01 10 11 SOURCEDESTINATION VRAMVRAM ROMVRAM Extend RAMVRAM VRAMExtend RAM
Bit 0 : Compound/overwrite bit
BIT 0 1 Compound mode Overwrite mode STATUS
- 38 -
SM8521
How to overturn a character in right and left. 4-dot data is transfered as a unit, from ROM to VRAM or VRAM to VRAM. ROM is composed of 8
ROM
bits. In case of "Increment x" is effective, 8-bit data is transfered as shown below.
VRAM
Bit 7
dot3 dot2 dot1 dot0
0
Bit 7
dot3 dot2 dot1 dot0
0
On the other hand, in case of "Decrement x" is effective, 8-bit data is transferred as shown below.
In each 4-dot data is automatically swapped in right and left.
VRAM
Bit 7
dot3
ROM
dot2 dot1 dot0
0
Bit 7
dot0 dot1 dot2 dot3
0
Position of all specified dots, maximun 256, is overturned with right and left in horizontal. The
heart of their X coordinates becomes an axis of symmetry.
DMX1 (Source X-coordinate register)
Bit 7
0
DMX17 DMX16 DMX15 DMX14 DMX13 DMX12 DMX11 DMX10
DMY1 (Source Y-coordinate register)
Bit 7
0
DMY17 DMY16 DMY15 DMY14 DMY13 DMY12 DMY11 DMY10
DMDX (X-width register (X-width-1))
Bit 7
0
DMDX7 DMDX6 DMDX5 DMDX4 DMDX3 DMDX2 DMDX1 DMDX0
DMDY (Y-width register (Y-width-1))
Bit 7
0
DMDY7 DMDY6 DMDY5 DMDY4 DMDY3 DMDY2 DMDY1 DMDY0
DMX2 (Destination X-coordinate register)
Bit 7
0
DMX27 DMX26 DMX25 DMX24 DMX23 DMX22 DMX21 DMX20
DMY2 (Destination Y-coordinate register)
Bit 7
0
DMY27 DMY26 DMY25 DMY24 DMY23 DMY22 DMY21 DMY20
- 39 -
SM8521
DMPL (Pallet register) DMPL register specifies gradation to dot data. When transferring, gradation data concerned with dot data of the DMPL register is stored to VRAM. Bit 7 0
COL31COL30 COL21 COL20 COL11 COL10 COL01 COL00
Example : When dot data color 2 (10B) is specified under the status of the DMPL register filled with 01B, bit 4 and 5 of the DMPL register are automatically selected. Dot data changes from color 2 (10B) to color 1 (01B). Then the dot data color 1 moves to specified VRAM.
Bits Bits Bits Bits
7 5 3 1
to to to to
6 4 2 0
: : : :
Dot Dot Dot Dot
data data data data
color color color color
0 1 2 3
ROM/VRAM
Dot data = color 2 (10B)
Color 3 DMPL
Color 2 01
Color 1
Color 0
VRAM
Dot data = color 1 (01B)
NOTE : Color 0-3 are not depth gradation. Depth of black and white on LCD is fixed by Gradiation control bit of the LCC register.
Fig. 18 How to Select Gradations
DMBR (ROM bank register) DMBR register specifies ROM's bank being transferred. (Organization of bank is 256 x 256 dots. Bank specifies external memory address irrespective of MMU.) Bit 7 0
DMBR6 DMBR5 DMBR4 DMBR3 DMBR2 DMBR1 DMBR0
Bits 7 to 2 : Set `0'. Bit 1 : Destination page A/B
BIT 0 1 CONTENT Destination page A Destination page B
Bit 0 : Source page A/B
BIT CONTENT Source page A Source page B 0 1
DMVP(DMVP register) DMVP register specifies a page (VRAM) in case of specifying VRAM to source and destination. Bit 7 0
SOUAB DESAB
- 40 -
SM8521
SOUND GENERATOR
The SM8521 supports two waveform generators concerning arbitrary waveform output channel and one noise generator channel. After each channel's signal is amplified through each variable register, a digital mixer mixes them into one and D/A outputs it.
Internal bus Waveform generator Internal bus D/A direct output channel
SG0
Scale counter
Address generator
Waveform memory
Digital mixer SG1 Waveform generator
D/A
Sound output
SG2
Noise sound generator (Random rectangular waveform)
Fig. 19 Sound Generator Block Diagram
* Waveform generator The data, 4-bit x 32 steps, stored in the waveform register (SGW0-15) is output at the timing of FCK (main clock) divided by time constant register. * Digital mixer 4-bit data generated from each generator is expanded to sixteen times as large as original 4-bit data. Those expanded data is added to one another after passing through digital attenuator (0, 1/32, 2/32, .... 31/32) of which attenuation rate is specified by output level control register. NOTE :
Attention to the sum total of each sound generator, not exceeding capacity of digital mixer.
* Noise sound register False noise, of which maximum frequency is based on cycle divided FCK (main clock) by time constant register, is output. * D/A direct output register (in digital mixer) When all sound generator 0, 1 and 2 are disable, the data stored in this register is directly effective as D/A input, provided that the data is stored in the SGDA register and both sound output enable register and D/A direct output enable registers are set. NOTE :
All 12 bits of each SG0, SG1 and SG2 must not be filled with 0. If all 12 bits become 0, D/A can not perform correct output.
- 41 -
SM8521
Sound Waveform Register
Sound waveform generator can outputs 16-tone wedge and 32-step sign waveform as shown below.
Step
01234567891111111111222222222233 0123456789012345678901
NOTE :
A period of one step is variable based on the value of Time constant register (SG0, SG1 and SG2 composed of 12 bits). The period can be lead from the formula shown below.
Period = fCK(n-1) Period : Time of one step : System oscillation frequency fCK n : Value of Time constant register
- 42 -
SM8521
In order of Low and High, each 4-bit data is specified. Each SG0 and SG1 waveform register stores 4-bit x 32-step data as shown below. Refer to SG0 and SG1 waveform registers in Fig. 9-3. The most significant bit of each 4-bit data indicates positive and negative. That means, range of each 4-bit data is -8 to +7. NOTE :
Waveform register read/write is possible only when SG is disable.
7 0 1 2 3 4 5 6 7 8 9 A B C D E F STEP1 STEP3 STEP5 STEP7 STEP9 STEP11 STEP13 STEP15 STEP17 STEP19 STEP21 STEP23 STEP25 STEP27 STEP29 STEP31
4
3 STEP0 STEP2 STEP4 STEP6 STEP8 STEP10 STEP12 STEP14 STEP16 STEP18 STEP20 STEP22 STEP24 STEP26 STEP28 STEP30
0
Fig. 20 Sound Waveform Register
D/A output level
+5.0 V
+2.5 V
Rump-up period
Rump-down period
Time
NOTES :
* Mute level of the D/A should be created by software. * Attenuate not to exceed capacity of D/A output level (0-5 V) by software. * To avoid pop-noise, make rump-up and down period by software.
Fig. 21 Example of D/A Output
- 43 -
SM8521
Registers
SGC (Control register) Bit 7
SONDOUT -
0
DIROUT SG2OUT SG1OUT SG0OUT
SG0W0-15, SG1W0-15 (Waveform register 0-15) Bit 7 0
SGxWy7 SGxWy6 SGxWy5 SGxWy4 SGxWy3 SGxWy2 SGxWy1 SGxWy0
(x = 0, 1)(y = 0 to 15) Bits 7 : Sound output enable Bits 6 to 4 : Set `0'. Bit 3 : D/A direct output enable Bit 2 : SG2 output enable Bit 1 : SG1 output enable Bit 0 : SG0 output enable SG0L, SG1L (Output level control register ; 0, 1/32, 2/32...31/32) Bit 7 0
SGxL4 SGxL3 SGxL2 SGxL1 SGxL0
Bits 7 to 4 : Waveform data Low order Bits 3 to 0 : Waveform data High order SG2L (Output level control register ; 0, 1/32, 2/32...31/32) Bit 7 0
SG2L4 SG2L3 SG2L2 SG2L1 SG2L0
Bits 7 to 5 : Set `0'. The value of output level control register decides the digital attenuation rate. SG2TL (Time constant register ; Low) Bit 7 0
SG2TL7 SG2TL6 SG2TL5 SG2TL4 SG2TL3 SG2TL2 SG2TL1 SG2TL0
(x = 0, 1) The value of output level control register decides the digital attention rate. SG0TL, SG1TL (Time constant register ; Low) Bit 7 0
SGxTL7 SGxTL6 SGxTL5 SGxTL4 SGxTL3 SGxTL2 SGxTL1 SGxTL0
(x = 0, 1) SG0TH, SG1TH (Time constant register ; High) Bit 7 0
SGxTH3 SGxTH2 SGxTH1 SGxTH0
SG2TH (Time constant register ; High) Bit 7 0
SG2TH3 SG2TH2 SG2TH1 SG2TH0
Bits 7 to 4 : Set `0'. A period of one step is variable based on the value of Time constant register (SG2TL and SG2TH composed of 12 bits). SGDA (D/A direct output register ; write only) Bit 7 0
SGDA7 SGDA6 SGDA5 SGDA4 SGDA3 SGDA2 SGDA1 SGDA0
(x = 0, 1) Bits 7 to 4 : Set `0'. A period of one step is variable based on the value of Time constant register (SG0TL, SG0TH, SG1TL and SG1TH composed of 12 bits.)
The value of SGDA register directly transfers digital mixer. NOTES :
* Time constant register must be written by "MOVW" instruction. * Each time constant register must not be filled with all "0" or only the Low significant bit is "1".
- 44 -
SM8521
MMU
The SM8521 supports an MMU used to external memory area expansion.
15 CPU address
Memory area 1000H-9FFFH, can be expanded to 2M-byte in each 8k-byte unit.
13 12 0
7 MMU0 (0000H-1FFFH) MMU1 (2000H-3FFFH) MMU2 (4000H-5FFFH) MMU3 (6000H-7FFFH) MMU4 (8000H-9FFFH)
0
20 External memory address
13 12
0
Fig. 22 An Example of MMU Switching Flow and Mapping
MMUx is selected depends on CPU address. NOTE :
CPU can not access lower 4 k-byte of MMU0 because of occupied by internal RAM and register file. On the other hand, each 8 k-byte of external ROM is accessible as DMA's address.
- 45 -
SM8521
000000H
0000H Internal I/O / RAM 0400H 1000H 2000H 4000H 8 k-byte 6000H 8 k-byte 8000H 8 k-byte A000H E000H FFFFH 4 k-byte 8 k-byte NOTES External ROM/Flash External ROM/Flash External ROM/Flash External ROM/Flash VRAM Extend I/O Extend RAM ROM/Flash
1FFFFFH
Fig. 23 MMU Mapping
NOTES :
* At reset, MMU0 is disable and internal ROM is enable. (1000H-1FFFH). At setting data into MMU0 once, internal ROM becomes disable and MMU0 becomes enable. * In case of changing to external ROM mode by putting some data into MMU register, use Immediate R in "MOV" instruction (MOV R, r or MOV R, R). Data in the next internal ROM address will be fetched at the same time of executing the instruction. Only one byte instruction can be followed when setting data to MMU0 register.
0000H Internal I/O / RAM 0400H 1000H 4 k-byte 2000H 8 k-byte 4000H 8 k-byte 6000H 8 k-byte 8000H 8 k-byte A000H VRAM E000H Extend I/O Extend RAM FFFFH In case of MMU0 is disable (At reset) External ROM/Flash External ROM/Flash External ROM/Flash Internal ROM External ROM/Flash
0000H Internal I/O / RAM 0400H 1000H 4 k-byte 2000H 8 k-byte 4000H 8 k-byte 6000H 8 k-byte 8000H 8 k-byte A000H VRAM E000H Extend I/O Extend RAM FFFFH In case of MMU0 is enable External ROM/Flash External ROM/Flash External ROM/Flash External ROM/Flash External ROM/Flash
Fig. 24 Comparison Figure MMU 0 between Disable and Enable
- 46 -
SM8521
UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER (UART) INTERFACE
SM8521 supports 1-channel universal asynchronous receiver and transmitter interface (UART) . The UART interrupt has the following features. * Transmitter and receiver are independent each other, full duplex communication possible. * Receiver is consisted of duplex buffer, able to receive data continuously. * The dedicated register for baud rate generator is built-in.
* It is possible to choose transfer format as following. * Stop bit : 1-bit/2-bit * Parity bit : even parity/odd parity/no parity * Receive error can be detected. * Frame error * Parity error * Overrun error NOTE :
UART baud rate is fixed at [Timer 0 output/32]. Regarding Timer 0, refer to "8-Bit Timer Register TM0C".
Interrupt request signal to bit IR03 (bit 3 : IR0) P70/RXD
P
Receive data shift register
Receive control
Receiver data register URTR
Status register URTS
Data bus
Transmit control
TXD
Transmit data register URTT
P
Control register URTC
Timer 0 output
Divider (Divided by 16) : A control register mapped by register file
Fig. 25 UART Block Diagram
- 47 -
SM8521
UART Transmit Data Register (URTT)
Transmit data register URTT is an 8-bit write only register which stores the UART transmit data. When the transmission operation starts, the content of this register LSB first is output from P71/TxD pin.
Bit 3 : Frame error bit (FE)
BIT 0 CONTENT Clear condition (1) While reading the status register URTS (2) Hardware reset Set condition 1 (1) While frame error occurs (stop bit = `0' is detected.) at receive data.
UART Receive Data Register (URTR)
Receive data register URTR is an 8-bit read only register which stores the UART receive data. When the receive operation starts, the receive data LSB first will be moved into the receive data shift register from P70/RxD pin. Once the receive operation is complete, the content of the receive data shift register is loaded into this receive data register URTR (duplex buffer).
Bit 2 : Parity error bit (PE)
BIT Clear condition 0 (1) While reading the status register URTS (2) Hardware reset Set condition (1) Parity error occurs at receive data CONTENT
1
UART Status Register (URTS)
Status register (URTS) is an 8-bit read only register containing the flags of the UART interface transmit/ receive status. Bit 7
RBSY OR FE
Bit 1 : Transmit data register empty bit (TDRE)
BIT 0 CONTENT Clear condition (1) While writing to transmit data register URTT Set condition (1) While having finished transmitting operation. (2) Hardware reset
0
PE TDRE TDRF
Bits 7 to 6 : Set `0' Bit 5 : Receiver busy bit (RBSY)
BIT 0 1 CONTENT UART receiver is other than the following. UART receiver processing incoming data.
1
Bit 0 : Receiver data register full bit (RDRF)
BIT CONTENT Clear condition (1) While reading from receive data register URTR (2) Hardware reset Set condition (1) While receive data is transferring to receive data register URTR from receive data shift register.
Bit 4 : Overrun error bit (OR)
BIT Clear condition 0 (1) While reading the status register URTS (2) Hardware reset Set condition (1) While overrun error occurs (the next receive is complete under the bit RDRF = `1'. ) at receive data CONTENT
0
1
1
- 48 -
SM8521
UART Control Register (URTC)
Control register URTC is an 8-bit readable/writable register specifying transfer format setting and transmit/receive operation controlling. Bit 7
TE RE
0
PEN EOP SBL
Bit 3 : Receive enable bit (RE) Setting the bit RE to `1', starts the built-in baud rate generator and the interface enters receivable status. In such status, if the start bit (= `0') is detected, then will start the receive operation. If the bit RE clears to `0', the receiver will be initializated.
BIT 0 1 Receiver disable Receiver enbable (built-in baud rate generator operates) CONTENT
Bits 7 to 5 : Set `0'. Bit 4 : Transmit enable bit (TE) Setting the bit TE to `1', starts the built-in baud rate generator and the interface enters transmissible status. In such status, if a transmit data is written to the transmit data register URTT, then will start the transmission operation. If the bit TE clears to `0', the transmitter will be initializated.
BIT 0 1 CONTENT Transmitter disable Transmitter enable (built-in baud rate generator operates)
Bit 2 : Parity enable bit (PEN)
BIT 0 1 CONTENT Transmit : the data with parity bit Receive : parity enable Transmit : the data without parity bit Receive : parity disable
Bit 1 : Even/odd parity bit (EOP)
BIT 0 1 CONTENT Even parity Odd parity
Bit 0 : Stop bit length bit (SBL)
BIT 0 1 Stop bit : 1 bit Stop bit : 2 bits CONTENT
- 49 -
SM8521
Transfer Format
According to setting stop bit and parity bit by control register URTC, transfer format indicated by Fig. 26 can be selected.
URTC PEN (bit 2) 0 0 1 1 SBL (bit 0) 0 1 0 1 ST ST ST ST bit 0 bit 0 bit 0 bit 0 bit 1 bit 1 bit 1 bit 1 bit 2 bit 2 bit 2 bit 2
Transfer Format
(Transfer Direction) bit 3 bit 3 bit 3 bit 3 bit 4 bit 4 bit 4 bit 4 bit 5 bit 5 bit 5 bit 5 bit 6 bit 6 bit 6 bit 6 bit 7 bit 7 bit 7 bit 7 P P STP STP STP STP STP STP
ST : start bit, P : parity bit, STP : stop bit
Fig. 26 Transfer Format
ST
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
parity
STP STP
Fig. 27 8-Bit Mode Transfer Format (Example for Parity Added and 2 Stop Bits)
- 50 -
SM8521
INSTRUCTION SET
The instruction set of the SM85CPU has the following characteristics : * The instruction set is the result of subtle design and consists of 67 types of basic instructions. * The powerful bit manipulation instructions includes plural bits transfer, logical operation between bits, and the bit test and jump instructions that incorporates a test and condition branch in the same instruction. * There are transfer, operation and conditional branch instructions for 16-bit. The actions of transfer, operation and long jump for word data can be processed in High speed. * There are arithmetic instructions for multiplication and division. Multiplication : 8-bit x 8-bit16-bit Division : 16-bit x 16-bit16-bit remaining 8-bit * 23 types of memory addressing mode * By variety of memory addressing modes, the accessing to RAM, ROM, and register file can be operated .
Definition of Symbols
SYMBOL PC SP @SP PS0 PS1 C Z S V D H BF I dst src cc EXPLANATION Program counter Stack pointer Indirect stack pointer Processor status 0 Processor status 1 Carry flag Zero flag Sign flag Overflow flag Decimal complement flag Half carry flag Bit flag Interrupt enable Destination Source Condition code
Instruction Summary
Load Instructions
INSTRUCTION OPERAND CLR MOV MOVM MOVW POP POPW PUSH PUSHW dst dst, src dst, IM, src dst, src dst dst src src FUNCTION dst0 (Clear) dstsrc (Move) dst(dst AND IM) OR src (Move Under Mask)
dstsrc (Move Word)
dst@SP, SPSP+1 (Pop from Stack) dst@SP, SPSP+2 (Pop Word from Stack) SPSP-1, @SPsrc (Push to Stack) SPSP-2, @SPsrc (Push Word to Stack)
- 51 -
SM8521
Arithmetic Operation Instructions
INSTRUCTION OPERAND ADC ADCW ADD ADDW CMP CMPW DA DEC DECW DIV EXTS INC INCW MULT NEG SBC SBCW SUB SUBW dst, src dst, src dst, src dst, src dst, src dst, src dst dst dst dst, src dst dst dst dst, src dst dst, src dst, src dst, src dst, src FUNCTION dstdst+src+C (Add With Carry) dstdst+src+C (Add Word With Carry) dstdst+src (Add) dstdst+src (Add Word) dst-src (Compare) dst-src (Compare Word) dstDA dst (Decimal Adjust) dstdst-1 (Decrement) dstdst-1 (Decrement Word) dstdst/src, srcdst MOD src (Divide) Extend sign (Extend Sign) dstdst+1 (Increment) dstdst+1 (Increment Word) dstdst x src (Multiply) dst -dst (Negate) dstdst-src-C (Subtract With Carry) dstdst-src-C
(Subtract Word With Carry)
Logical Operation Instructions
INSTRUCTION OPERAND AND ANDW COM OR ORW XOR XORW dst, src dst, src dst dst, src dst, src dst, src dst, src FUNCTION dstdst AND src (Logical And) dstdst AND src (Logical And Word) dstNOT dst (Complement) dstdst OR src (Logical OR) dstdst OR src (Logical OR Word) dstdst XOR src (Logical Exclusive OR) dstdst XOR src
(Logical Exclusive OR Word)
Program Control Instructions
INSTRUCTION OPERAND BBC BBS BR CALL src, dst src, dst cc, dst dst FUNCTION
If src = 0 then PCPC+dst (Branch on Bit Clear) If src = 1 then PCPC+dst (Branch on Bit Set) If cc = true then PC PC+dst (Branch)
SPSP-2, @SPPC, PCdst (Call Subroutine) SPSP - 2, @SPPC, PCdst (Short Call Subroutine) rr-1, if r 0 then
CALS
dst
dstdst-src (Subtract) dstdst-src (Subtract Word) DBNZ r, dst
PCPC+dst (Decrement and Branch on Non-Zero) PS1@SP, SPSP+1, PC@SP, SPSP+2 (Return from Interrupt) If cc = true,then PCdst (Jump) PC@SP, SPSP+2
(Logical Exclusive OR Word)
IRET
JMP RET
cc, dst
- 52 -
SM8521
Bit Operation Instructions
INSTRUCTION OPERAND BAND BCLR BCMP BMOV BOR BSET BTST BXOR BF, src dst BF, src dst, src dst, src dst dst, src BF, src FUNCTION BFBF AND src (Bit And) dst0 (Bit Clear)
BF-src (Bit Compare)
dstsrc (Bit Move) dstBF OR src (Bit OR) dst1 (Bit Set) dst AND src (Bit Test) BFBF XOR src (Bit Exclusive OR)
Rotate and Shift Instructions
INSTRUCTION OPERAND RLC RR RRC SLL SRA SRL SWAP dst dst dst dst dst dst dst FUNCTION
(Rotate Left through Carry)
(Rotate Right)
(Rotate Right through Carry)
(Shift Left Logical) (Shift Right Arithmetic) (Shift Right Logical) (Swap Nibbles)
CPU Control Instructions
INSTRUCTION OPERAND FUNCTION C0 (Clear Carry Flag) CLRC COMC DI EI HALT NOP SETC STOP CNOT C (Complement Carry Flag) I0 (Disable Interrupt)
I1 (Enable Interrupt)
Move to HALT mode (Halt CPU) No Opreration (No Opreration) C1 (Set Carry Flag) Go to STOP mode (Stop CPU)
- 53 -
SM8521
Addressing Mode
There are 23 types of addressing mode to perform memory accessing in SM85CPU. The relationships between the addressing modes and the operand are shown in the following table 5.
Table 5 Addressing Mode Summary
NAME Implied Register Register pair Register file Register file pair Register indirect Register indirect auto increment Register indirect auto decrement Register index Register pair indirect Register pair indirect r rr R RR @r (r)+ -(r) n(r)2 @rr (rr)+ -(rr) nn(rr)3 @nn(r)2 IM IML b p RA DA DAs DAp @DA r = R0-R7 r = RR0, RR2, ... , RR14 R = 0 to 255 (R0-R15) R = 0, 2, ... 254 (RR0, RR2, ... , RR14) r = R0-R7 r = R0-R7 r = R0-R7 n = 00H-FFH, r = R1-R7 rr = RR0, RR2, ... , RR14 rr = RR0, RR2, ... , RR14 rr = RR0, RR2, ... , RR14 nn = 0000H-FFFFH rr = RR2, RR4, ... , RR14 nn = 0000H-FFFFH r = R1-R7 IM = 00H-FFH IML = 0000H-FFFFH b = 0 to 7 SYMBOL Range Operand 1
To specify the carry(C) and interrupt enable (I) in the instruction code.
General register [byte] General register [word] Register file (0000H-007FH) and (0080H-00FFH) [byte] Register file (0000H-007FH) and (0080H-00FFH) [byte] Memory (0000H-00FFH) [byte] Memory (0000H-00FFH) [byte] Memory (0000H-00FFH) [byte] Memory (0000H-00FFH) [byte] Memory (0000H-FFFFH) [word/byte] Memory (0000H-FFFFH) [word/byte] Memory (0000H-FFFFH) [word/byte] Memory (0000H-FFFFH) [word/byte] Memory (0000H-FFFFH) [word] The immediate data in the instruction code [byte] The immediate data in the instruction code [word] Register file (0000H-007FH) and memory (0080H-00FFH, FF00H-FFFFH) [bit] (1 bit of 1 byte pointed by R, n(r) and DAp) Register file (0010H-0017H) [byte] Program memory (1000H-FFFFH) Memory (0000H-FFFFH) [byte] Program memory (1000H-1FFFH) Program memory (FF00H-FFFFH) [byte] Memory (0000H-FFFFH)
auto increment
Register pair indirect auto decrement Register pair index Index indirect Immediate Immediate long Bit Port Relative Direct Direct short Direct special page Direct indirect
1 The data indicated by [ 2 R0 can not be used. 3 RR0 can not be used.
PC - 128 to PC + 127 DA = 0000H-FFFFH DAs = 1000H-1FFFH DAp = FF00H-FFFFH DA = 0000H-FFFFH
] is the unit of possible to use in Load and Arithmetic Instructions.
- 54 -
SM8521
SYSTEM CONFIGURATION EXAMPLE
* Electronic organizer
5V VLCD 5V
SM85CPU
Common driver LH1527
RAM (1 k-byte) ROM (4 k-byte) SRAM (8/16k-byte) LCDC/DMA Timer * Clock * Watchdog timer AMP PC IR PIO Sound generator UART MMU Segment driver LH1528 VLCD 5V
LCD panel (200/160 x 100/160/200-dot)
8-bit
MROM Flash SRAM Key matrix/touch key MAX. 2 M-byte
SRAM
MAX. 8 k-byte
- 55 -
SM8521
128 QFP (QFP128-P-1420)
102 103
65
64
(1.3)
0.5 TYP.
0.20 0.08
0.08
M
0.15
0.05
14.0 0.2
16.6 0.3
128 1 (1.3) 20.0 0.2 22.6 0.3
39 38 (1.3) (1.3) 0.9 0.1 0.1 1.95 0.2 Package base plane
- 56 -
0.10
15.6 0.2

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